As contact area decreases with feature
size, thermal resistivity increases, and the
volume of phase-change material that must
be melted to completely block current
flow decreases. Specifically, as feature size
scales down (1/k), contact area decreases
quadratically (1/k2
). Reduced contact area
causes resistivity to increase linearly (k),
which in turn causes programming current
to decrease linearly (1/k). These effects enable
not only smaller storage elements but
also smaller access devices for current injection.
At the system level, scaling translates
into lower memory-subsystem energy.
Researchers have demonstrated this PCM
scaling mechanism in a 32-nm device
prototype.1,3