The power reduction techniques described thus far only address active power. In standby, however, an additional source of power, leakage power, PLKG, becomes significant. PLKG refers to idle-mode current that flows while logic circuits are in a high or low state, and it is particularly prominent in advanced technologies, where, by design, Vt is low in order to maximize performance. As shown in Figure 6, even when VGS is reduced to zero, some finite leakage current continues to flow. To eliminate it, the supply voltage must also be gated using high-threshold header devices that have much lower leakage current (64, 65). Of course, header device control, as well as power-supply voltage (VVDD) recovery after standby, has some associated energy overhead, EOverhead. A simulation of EOverhead, as well as the circuit's leakage energy, ELKG, is shown in Figure 6 for a finite impulse response (FIR) filter implementation after entering standby (at t = 0). Power-gating only saves energy in this example if the duration of the standby mode exceeds the break-even time of 46 μs, and it should not be applied for shorter periods of inactivity.
Minimum energy sub-threshold operation.When aggressive voltage scaling is employed, such that the supply voltage is near or below the MOSFET threshold voltage, the resulting leakage energy becomes significant even during normal circuit operation because the circuit delay increases exponentially. In this scenario, the power supply cannot be gated until the operation is complete, and the leakage power integrates over the operating time. Consequently, ELKG is given by Equation 5: