Abstract
-
Now a days the computer architecture
development resources away fro
m the uniprocessor technology to
multiprocessor technology. The exis
t
ed multiprocessor core
architecture has faced a problem with thread interdependencies
due to lack of internal synchronization of multi
-
processor
.
For
this purpose the designed concurrent
computing multiprocessor
core architecture performs both pa
r
allel and distributed
computations simultaneously. The interdependencies are
eliminated by using pa
r
allel computations and shared data
problems are annihilated by duplicated memories. The main
a
d
vantage of designed architecture is integrated Multi Universal
Asynchronous Receiver and Transmitter (MUART). The Multi
Universal Asynchronous R
e
ceiver and Transmitter (MUART) to
enable the data transmission and reception concurrently on the
FPGA. It perf
orms both transmission and reception of data by
concurrent computational technique. The area, speed and power
of designed architecture are analyzed using Xilinx platform.