To understand how the receiver extracts encoded data, assume it has a
clock running at a multiple of the baud rate (e.g. 16x) starting from an idle
state as illustrated in Figure 5. The receiver “samples” its RX signal until it
detects a high-low transition. It then waits 1.5 bit periods (24 clock periods)
to sample its RX signal at what it estimates to be the center of data bit 0.
The receiver then samples RX at bit-period intervals (16 clock periods) until
it has read the remaining 7 data bits and the stop bit. From that point the
process repeats. Successful extraction of the data from a frame requires that,
over 10.5 bit periods, the drift of the receiver clock relative to the transmitter
clock be less that 0.5 periods in order to correctly detect the stop bit.