Each of the physical processor cores in these designs provides two virtual cores, one
considered Non-secure and the other Secure, and a mechanism to robustly context
switch between them, known as monitor mode. The value of the NS bit sent on the main
system bus is indirectly derived from the identity of the virtual core that performed the
instruction or data access. This enables trivial integration of the virtual processors into
the system security mechanism; the Non-secure virtual processor can only access
Non-secure system resources, but the Secure virtual processor can see all resources.