Bitsliced Implementation of the ShiftRows and the Inverse ShiftRows In our way of state bits rearrangement,
ShiftRows and Inverse ShiftRows correspond to rotate bits in lanes, which are depicted in Figure 3b. Thus that
needs to rotate high half and low half of 8-bit registers separately in our implementation. We implement this by
logical AND (AND), logical shift left and right (LSL and LSR), bit load from the T flag in SREG to a bit in
register (BLD) and bit store from bit in register to T flag in SREG (BST) instructions.
With respect to Scenario 1, it takes 419 = 76 instructions to implement ShiftRows (or Inverse ShiftRows)
per state. With respect to Scenario 2, it takes 419+2 = 78 instructions to implement ShiftRows (or Inverse
ShiftRows) per 2 states (thus 39 instructions per state).
Bitsliced Implementation of the ShiftRows and the Inverse ShiftRows In our way of state bits rearrangement,ShiftRows and Inverse ShiftRows correspond to rotate bits in lanes, which are depicted in Figure 3b. Thus thatneeds to rotate high half and low half of 8-bit registers separately in our implementation. We implement this bylogical AND (AND), logical shift left and right (LSL and LSR), bit load from the T flag in SREG to a bit inregister (BLD) and bit store from bit in register to T flag in SREG (BST) instructions.With respect to Scenario 1, it takes 419 = 76 instructions to implement ShiftRows (or Inverse ShiftRows)per state. With respect to Scenario 2, it takes 419+2 = 78 instructions to implement ShiftRows (or InverseShiftRows) per 2 states (thus 39 instructions per state).
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