The baseline processor model integrates eight cores and supports a DDR3-1066 memory subsystem with four independent, address-interleaved memory channels. Our memory subsystem model (DIMM structure, timing, and power) follows the Micron DDR3 DRAM specification [2, 3, 4], including refresh. The micro-architectural features of the baseline processor are shown in Table 1; the parameters of the L2 cache, the memory system, and the DDR3 SDRAM power model are shown in Tables 2 and 3. We implement our model by extending the SESC simulation environment appropriately [27].