Successive approximation ADC.A typical implementation of a SAR ADC is shown in Figure 11a, where the sample and hold (S/H) and digital-to-analog converter (DAC) are implemented as one capacitor array; during input acquisition, the negative of the input voltage is sampled on the top-plates, and, subsequently, during the conversion the binary weighted capacitors are successively switched between ground and VDD by a digital controller, performing a binary search that eventually converges to the digital output code. Importantly, all components, except the comparator, are either passive or digital. Accordingly, the voltage scaling and clock-gating approaches discussed in Section 3.2.2 enable micropower SAR implementations (73, 75).