◆ An SMP consists of multiple similar processors within the same computer,
interconnected by a bus or some sort of switching arrangement. The most
critical problem to address in an SMP is that of cache coherence. Each
processor has its own cache and so it is possible for a given line of data to be
present in more than one cache. If such a line is altered in one cache, then
both main memory and the other cache have an invalid version of that line.
Cache coherence protocols are designed to cope with this problem.