For QPSK demodulator , a coherent demodulator is taken as an example. In coherent detection technique the knowledge of the carrier frequency and phase must be known to the receiver. This can be achieved by using a PLL (phase lock loop) at the receiver. A PLL essentially locks to the incoming carrier frequency and tracks the variations in frequency and phase. For the following simulation , a PLL is not used but instead we simple use the output of the PLL. For demonstration purposes we simply assume that the carrier phase recovery is done and simply use the generated reference frequencies at the receiver (cos(ωt)) and (sin(ωt)).
In the demodulator the received signal is multiplied by a reference frequency generators (cos(ωt)) and (sin(ωt)) on separate arms (in-phase and quadrature arms). The multiplied output on each arm is integrated over one bit period using an integrator. A threshold detector makes a decision on each integrated bit based on a threshold. Finally the bits on the in-phase arm (even bits) and on the quadrature arm (odd bits) are remapped to form detected information stream. Detector for in-phase arm is shown below. For quadrature arm the below architecture remains same but sin(ωt) basis function must be used instead.