I2C Overview
• Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers.
• It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer.
• Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standardmode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode.
• On-chip filtering (50 ns) rejects spikes on the bus data line to preserve data integrity.
• The number of ICs that can be connected to the same bus segment is limited only by the maximum bus capacitive loading of 400 pF. Slide 24 Originally, the I2C bus was designed to link a small number of devices on a single card, such as to manage the tuning of a car radio or TV. The maximum allowable capacitance was set at 400 pF to allow proper rise and fall times for optimum clock and data signal integrity with a top speed of 100 kbps. In 1992 the standard bus speed was increased to 400 kbps, to keep up with the ever-increasing performance requirements of new ICs. The 1998 I2C specification, increased top speed to 3.4 Mbits/sec. All I2C devices are designed to be able to communicate together on the same two-wire bus and system functional architecture is limited only by the imagination of the designer.