When have a liI want to provide a little more clarification. What I am looking for is a breakdown (or Pareto) of the ET error codes for Bin A ET failures and I would like to compare them between NRM and STST wafers. I think the pareto you sent was NRM only, but I'm not sure. If so, please let me know and then add a second pareto for STST. Otherwise, please separate the data by wafer site. Thanks again.