four-core power results are shown in Figure 10b with
the power breakdown in detail. Since Half-DRAM-1Row has
almost the same runtime as the baseline, its power is given
so that we can concentrate on the power reduction from activation.
As shown in the figure, the power efficiency varies
among the benchmarks. For instance, test1 and test6 have
significant power reduction, which is up to 9.1% and 10%,
respectively. In contrast, the power reduction from test3 and
test9 is relatively small (5.8% and 7%). The effect of fine-grain
activation in Half-DRAM is mainly determined by the intensity
of activations at runtime. From Figure 10b, it is obvious
that the activation power in test1 is big enough to reflect the
power efficiency of Half-DRAM. On the other hand, the power
gain is limited because the high buffer hit rate can effectively
amortize the activation power, like what happens in test3. In
general, Half-DRAM-1Row can achieve 8.4% improvement
on power efficiency over the baseline.