By the Way, the delay time of the operation of each circuit is not 0 in the DC/DC converter having the above described con?guration. Accordingly, for example, if the time period from When the comparator 12 generates a reset pulse till When the oscillator 2 generates a set pulse is short, the behavior of the latch circuit 5 becomes unstable. As a result, the sWitches S1 and S1 cannot possibly be driven. Such a situation occurs, for example, When the interval betWeen the times T12 and T13 is short in FIG. 8. Explained beloW is the con?guration for preventing such a situation.