At the core of this camera we find 2 B&W WDR NSC1005 logarithmic sensors that are slaves to the same controller.
The general specifications of the sensors are given by figure 1. The NSC1005 can deliver constant contrast
sensitivity over 140 dB of dynamic range. Both sensors differential analog outputs are connected to 12 bits differential
ADCs. In this design a FPGA generates all the sensors control signals (Vsync, Vck, Hsync, Hck, RST, RD1 and RD2)
for both sensors resulting in a pixel level synchronization. The digitized left and right pixels levels are then sent to the
FPGA. The FPGA will pack the 12 bits left and right channels to create a single 24 bits channel that is sent to a host
PC (see fig. 2).