Fig. 4 shows the block diagram of the SPARC Core. Each
SPARC core (SPC) implements the 64-bit SPARC V9 instruction
set while supporting concurrent execution of eight threads.
Each SPC has one load/store unit (LSU), two Execution units
(EXU0 and EXU1), and one Floating Point and Graphics Unit
(FGU). The Instruction Fetch unit (IFU) and the LSU contain an
8-way 16 kB Instruction cache and a 4-way 8 kB Data cache respectively.
Each SPC also contains a 64-entry Instruction-TLB
(ITLB), and a 128-entry Data-TLB (DTLB). Both the TLBs are
fully associative. The memory Management Unit (MMU) supports
8 K, 64 K, 4 M, and 256 M page sizes and has Hardware