2. FIFO architecture
There are two types of FIFO designs and architectural schemes: serial and parallel [7], [8], [9] and [10]. The serial FIFO (such as shift register) that works by fall-through principle (or pipeline) was the first FIFO generation as shown in Fig. 2. However, the architectures of conventional FIFOs are constantly being improved. Currently, most of the FIFOs used are of parallel type, which are faster than serial FIFO [11]. This trend is acceptable in network on chip due to two main reasons. The first reason is related to the fall through concept where the new arrival flit is store at the tail location of FIFO, and at each shift request it is shifted one location (slot) toward the head of queue. In this way, all the stored flits should be shifted through all the storage locations at each request. This concept has three drawbacks of long full-through delay, bubble cells and high dynamic power consumption. The first drawback is due the fact that when the FIFO capacity is increased, its fall-through time will increase leading to linger latency of FIFO [11]. In fact, the minimum latency of a FIFO depends on the depth of physical FIFO rather than the number of stored items. The second drawback is due to the existence of bubble cells in the FIFO as shown in Fig. 2. The bubble cells can occur when the data input/output rates are different.