The arbiter plays a crucial role in the split bus architecture.
Not only does it grant bus accesses to compatible bus transactions, it also controls all splitters to establish proper data propagation paths for those granted bus transactions. The speed of
bus arbitration is also an important factor of the bus performance, because pending communication requests have to wait
until they obtain bus access signals. The long arbitration delay
can be alleviated by pipelined arbitration; however, this may
lead to an increase in communication latency.
Our arbiter implementation for a split bus with three segments is shown in the upper portion of Fig. 3. ‘SC’ in the figure refers to ‘Splitter Controller’. The arbiter performs two
levels of arbitration. The first level arbitration can be performed by any traditional arbitration method (e.g. prioritybased, TDMA), and only one module is selected as the first
level arbitration winner. The second level arbitration searches
for compatible communication requests and generates the bus
access grant signals and splitter control signals. As the first
level arbitration is well-understood, we focus only on the implementation of the second level arbitration.
In order to simplify the detection of compatible transactions,
the addresses of segments are assigned in the same order as
their relative positions on the bus. The i-th splitter is placed
between segment i and segment i+ 1. For each segment, there
is an agent in the arbiter. For convenience, the agent for the
segment, in which a module win the first level arbitration, is
called the ‘winner agent’. We first assume that there is only
one bus access request in each segment. We will present more
general cases later.
Two sets of bus segment usage information are passed between agents. The address of the highest segment occupied
is passed from agents of low segments to agents of high segments; the address of the lowest segment occupied is passed
in the opposite direction. These two sets of information are
identified as MaxSeg and MinSeg in Fig. 3.
The structure of an arbitration agent is shown in Fig. 4.
Agent i determines whether its pending communication can
access the bus based on MinSegi+1 if MinVldi+1 is asserted.
The assertion of MinVldi+1 indicates that agent i is before the
arbitration winner. Similarly, the bus access grant decision for
agent i is determined based on MaxSegi−1 when MaxVldi−1 is
asserted, which indicates that agent i is ordered after the arbitration winner. ArbWini for agent i is asserted only if agent i is
the winner agent. If the agent has a pending communication,
HighSegi is the address of the higher segment between segment i and the destination segment, and LowSegi is the address
of the lower segment. Otherwise the HighSegi and LowSegi
are set to the highest address and lowest address of all segments, respectively, to make its bus access grant impossible.
The assertion of signal Granti indicates that agent i is granted
for its pending communication. Signals Granti is determined
as follow: