III. RESULTS
A 12-1 V synchronous buck converter has been designed
utilizing three EPC 2015 eGaN enhancement mode HEMTs.
The converter is arranged with one high side switch and two
paralleled synchronous rectifiers. This combination has been
tested with two different layouts to see the effects of parasitic
inductance on the switching speed of the eGaN HEMTs. In the
first layout, the devices are arranged to minimize the layout
area. The layout is shown in Figure III. The maximum distance
along the ground return path is 15 mm. In the second layout,
the HEMTs are arranged in a line with enough space between
them to place vias on both sides of each pad not connected
to the top layer copper area. This layout is shown in Figure
III. The maximum ground return path length is also 15 mm.
However, ths board has been designed with approximately 50.8
um (2 mils) tall insulating layers between the copper layers.
Thus, the overall inductance loop is smaller than in the first
layout. In Figure 6(a), the dead band can be clearly seen in
the dip occuring around -12 ns with turn on occuring at 0 ns.
The voltage rises to 12 V in 5 ns. Additionally, the small
inductance of the layout of Figure III can be seen in that the
ripple voltage at turn-on only rises to a peak of 14 V. The
falling transition can be seen in Figure 6(b) with the turn-off
time at a maximum of 5 ns for a 5 A load and minimum of
2 ns for a 20 A load.
Turn on begins when the node voltage rises above 0 V and
stops when the node voltage exceeds 12 V. Turn off begins
when the node voltage drops below 11.25 V from the nominal
12 V input and stops when the output voltage drops below 0 V.
III. RESULTSA 12-1 V synchronous buck converter has been designedutilizing three EPC 2015 eGaN enhancement mode HEMTs.The converter is arranged with one high side switch and twoparalleled synchronous rectifiers. This combination has beentested with two different layouts to see the effects of parasiticinductance on the switching speed of the eGaN HEMTs. In thefirst layout, the devices are arranged to minimize the layoutarea. The layout is shown in Figure III. The maximum distancealong the ground return path is 15 mm. In the second layout,the HEMTs are arranged in a line with enough space betweenthem to place vias on both sides of each pad not connectedto the top layer copper area. This layout is shown in FigureIII. The maximum ground return path length is also 15 mm.However, ths board has been designed with approximately 50.8um (2 mils) tall insulating layers between the copper layers.Thus, the overall inductance loop is smaller than in the firstlayout. In Figure 6(a), the dead band can be clearly seen inthe dip occuring around -12 ns with turn on occuring at 0 ns.The voltage rises to 12 V in 5 ns. Additionally, the smallinductance of the layout of Figure III can be seen in that theripple voltage at turn-on only rises to a peak of 14 V. Thefalling transition can be seen in Figure 6(b) with the turn-offtime at a maximum of 5 ns for a 5 A load and minimum of2 ns for a 20 A load.Turn on begins when the node voltage rises above 0 V andstops when the node voltage exceeds 12 V. Turn off begins
when the node voltage drops below 11.25 V from the nominal
12 V input and stops when the output voltage drops below 0 V.
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