1. Clock rate – the logic speed of advanced
technologies will be significantly faster than
current generation,
2. Device density – linear feature size
reductions of close to two orders of
magnitude resulting in three to four orders
of magnitude gates per unit area,
3. Parallelism – systems implemented in
nanoscale technology will comprise orders
of magnitude greater number of local
execution sites and therefore will need to
exploit much higher degrees of algorithm
concurrency.
4. Latency – time of signal propagation
(measured in clock cycle time) through a
sequence of gates or equivalent physical
constructs across an entire component is
dramatically greater than that of
conventional system devices,
5. Reliability – much smaller devices may
break more easily; moreover, the probability
of single-point failures grows with the scale
of the system