The table in Fig. 22 illustrates the reduction in leakage and
corresponding increase in delay as the channel length was increased
above minimum for three different gates. 10% larger
channel length was chosen, resulting in, on an average, about
50% reduced leakage on a per-cell basis with about 14% impact
on the cell delay. High- (HVT) cells were considered as
well for leakage reduction. We did not have an unconstrained
choice of for the HVT cells. For HVT cells using the available
HVT transistors, the delay impact was much larger. As
a result, approximate calculations lead to the conclusion that
using HVT cells would have enabled substitution of only about
one-third of the number of gates as compared to using GBIAS
gates with 10% larger channel length. Hence, the GBIAS option
was chosen. This enabled about 77% additional leakage saving
as compared to using HVT cells. Cells in non-timing-critical
paths could be replaced by their GBIAS versions as long as this
did not result in any new noise, slew, or timing violations. Because
of footprint compatibility, the swapping was easily done
at the end of the design cycle without any timing, noise, or area
impact. This reduced leakage power by 10%–15%.