3.2. Simulation procedure
Fig. 3 shows the test setup used to verify the
effectiveness of the proposed testable FRWC. A logic
‘1’ at Vout indicates fault free operation else the
FRWC is faulty. Fault simulation was done by
using the PSPICE program with a model of the 0.5
μm CMOS process [6].
During self test operation, the waveforms and
generation circuits for the required control signals for
the switches S1-6 are illustrated in Fig. 4. In a SOC
environment, it is possible to obtain the necessary
control signals and capture the test response using
only existing resources such as a microprocessor and
scan path respectively.