During the transmission, the input signal
(TxD) can be referred to the signal CLR/T
which gives a synchronization to the baudrate
frequency selected in the control
register
Signal TxD is supplied to the FSK
modulator which generates two tones
centered at the selected channel with
deviation selected by the data in the
control register
The modulated signal is filtered by a programmable gm-C
bandpass filter (this reduces harmonics and, so, electromagnetics noise). The
resulting signal is supplied to the power
stage which drives through the pin ATOP1
and ATOP2 the line driver
The integrated
power line interface is composed of a
Class AB Double Ended (Bridge) stage,
which reduces even harmonics. Peak-topeak
output voltage is controlled through
the Automatic Level Control (ALC) by
means of RVL1, and RVL2 resistors
This
allows to maintains constant the output
signal amplitude despite of the power line
impedance variations. There is also a
current control loop which limits the peak
current delivered from the ATOP1 and
ATOP2 pins. The output current limit (up to
500mApeak) is set by means of a resistor
(RCL) connected to the CL pin, as shown
in Fig. 4 which corresponds to the rule: