External data traffic is a major source of power
consumption and the high amounts of data traffic are
required in rasterization stage as mentioned above. In
order to reduce the power consumption, researchers
especially focus on rasterization stage of the graphics
pipeline.
A promising technique to reduce the external data
traffic in the rasterization stage of the graphics pipeline
is tile-based rendering architecture [13, 14]. Fig.3 is the
proposed tile based 3D graphics rendering pipeline.