every 4 DR cycles is lost at the point of l2clk
–
drl2clk
crossing after traversing 24 mm on chip.
c) Placement of the pulses to enable data transfers needs
to meet setup and hold constraints for all conditions of
PVT. This involves creating timing budgets that are used
to drive the static timing analysis (STA) tools, as well as
con
fi
rm design points.
In Niagara2, all conditions are satis
fi
ed by the generation
and distribution of sync pulses as outlined in Fig. 14. The align
detection block generates an
aligned
pulse deterministically
using the fact that the reference and CMP clocks are phase