We assume our baseline system implements per-byte parity for the L1 cache, and SECDED ECC for the L2 and L3 caches to guard against soft errors. Since the on-die network uses 32-byte transfers, we implement SECDED ECC on 32-bytes in the L2 and L3 caches to protect against cache and network failures. Our single-core baseline runs at 850 mV with a 2.1 GHz frequency. The 2-core system runs at 700 mV with a 1.4 GHz frequency. The 4-core system runs at 590 mV with an 825 MHz frequency.