Only one pair of FPGA boards enabled efficient evaluations
of various interfaces by switching FMCs. Bandwidth measurements
of three data transmission sections were applied:
from the data generator to the prototype front-end DAQ, as
between FPGA boards; from the prototype front-end DAQ to
the evaluation system, as from FPGA boards to the computing
system; and to the entire evaluation system. Fig.3 shows the
block diagram of the evaluation system. The upper panel
shows Aurora and XAUI with SFP+ and QSFP+, which denote
the measured bandwidth from "Data generator" to Prototype
FE DAQ" which are composed of FPGA boards with FMCs.
The middle panel shows a PCIe data stream as a measurement
from the memory on the FPGA boards to the memory in the
computing system. The lower panel shows the entire DAQ
data stream from the sensor side to the computing platform.
Several data types, including fixed, incremental, and free-form
user data, were used. An error bit check was applied using bitby-
bit comparison.