Each cache is implementation-defined and can be one, two or four-way set associative cache of configurable size. They are physically indexed and physically addressed. The cache sizes are configurable with sizes in the range of 1 to 64KB, but the maximum clock frequency might be affected if you increase the cache sizes beyond 16KB. Both the instruction cache and the data cache are capable of providing two words per cycle for all requesting sources.
The cache way size can be varied between 1KB and 16KB in powers of 2. A 1KB cache size must be implemented as a 1 way cache, and a 2KB cache must be implemented as a 2 way cache. All other cache sizes must be implemented as 4 way set associative. The cache line length is fixed at eight words (32 bytes).
The maximum cache way size that the processor supports is 16KB. The minimum cache way size that the processor supports is 1KB. You can disable instruction cache and data cache together or instruction cache and data cache individually.