The BEAM-LEAD technique is a process developed to batch-fabricate (fabricate many at once) semiconductor circuit elements and integrated circuits with electrodes extended beyond the edges of the wafer, as shown in figure 1-27. This type of structure imposes no electrical difficulty, and parasitic capacitance (under 0.05 picofarad per lead) is equivalent to that of a wire-bonded and brazed-chip assembly. In addition, the electrodes may be tapered to allow for lower inductance, impedance matching, and better heat conductance. The beam-lead technique is easily accomplished and does not have the disadvantages of chip brazing and wire bonding. The feasibility of this technique has been demonstrated in a variety of digital, linear, and thin-film circuits.