used to improve performance of main memory and are now used inside modernDRAM chips as well as with caches. The Arm Cortex-A8 supports one to fourbanks in its L2 cache; the Intel Core i7 has four banks in L1 (to support up to 2memory accesses per clock), and the L2 has eight banks.Clearly, banking works best when the accesses naturally spread themselvesacross the banks, so the mapping of addresses to banks affects the behavior ofthe memory system. A simple mapping that works well is to spread the addressesof the block sequentially across the banks, called sequential interleaving. Forexample, if there are four banks, bank 0 has all blocks whose address modulo 4is 0, bank 1 has all blocks whose address modulo 4 is 1, and so on. Figure2.6shows this interleaving. Multiple banks also are a way to reduce power con-sumption both in caches and DRAM