B. Reduced-Complexity CNU Architecture
Using the proposed scheme, the CNU architecture consists of
two parts: a sorter that sorts out the incoming v-to-c messages
with the smallest nonzero LLRs, and a path constructor
that generates the c-to-v messages from the sorting results according
to Algorithm B. In the following, the architectures for
these two parts are presented.
1) Sorter: Fig. 3 shows the architecture for the sorter. The
shaded blocks denote RAM blocks. A pair of RAM S blocks,
denoted by RAM S0 and S1, are used to store the sorting results
in a ping-pong manner. Each RAM S can record
messages and the indices of the variable nodes they belong to.
Hence, the size of each RAM S is bits.
The finite field elements associated with zero LLRs are stored
into RAM Zero when they are read out from the v-to-c message
RAM. Accordingly, RAM Zero is of size bits. In addition,
these field elements are added up to compute by the
adder-register loop in the bottom right-hand corner of Fig. 3.
The sorting is carried out iteratively in rounds. In the first
round, the v-to-c messages with nonzero LLRs of the first
variable node are copied intoRAMS0. In addition, ’0’ is written
B. Reduced-Complexity CNU Architecture
Using the proposed scheme, the CNU architecture consists of
two parts: a sorter that sorts out the incoming v-to-c messages
with the smallest nonzero LLRs, and a path constructor
that generates the c-to-v messages from the sorting results according
to Algorithm B. In the following, the architectures for
these two parts are presented.
1) Sorter: Fig. 3 shows the architecture for the sorter. The
shaded blocks denote RAM blocks. A pair of RAM S blocks,
denoted by RAM S0 and S1, are used to store the sorting results
in a ping-pong manner. Each RAM S can record
messages and the indices of the variable nodes they belong to.
Hence, the size of each RAM S is bits.
The finite field elements associated with zero LLRs are stored
into RAM Zero when they are read out from the v-to-c message
RAM. Accordingly, RAM Zero is of size bits. In addition,
these field elements are added up to compute by the
adder-register loop in the bottom right-hand corner of Fig. 3.
The sorting is carried out iteratively in rounds. In the first
round, the v-to-c messages with nonzero LLRs of the first
variable node are copied intoRAMS0. In addition, ’0’ is written
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