How are these interrupts synchronized? When the CPU senses an interrupt, it does two
things: (1) it puts on a stack the contents of the PSW (Program Status Word), the code
segment register, and the instruction pointer register; and (2) it disables the interrupt
system so that other interrupts will be put off until the current one has been resolved.
The CPU uses the 8-bit number placed on the system bus by the interrupting device to
get the address of the appropriate interrupt handler from the interrupt vector table and
picks up execution at that address.
Finally, the interrupt handler reenables the interrupt system to allow higher-priority
interrupts to occur, saves any register it needs to use, and processes the interrupt as
quickly as possible.