them to place vias on both sides of each pad not connected
to the top layer copper area. This layout is shown in Figure
III. The maximum ground return path length is also 15 mm.
However, ths board has been designed with approximately 50.8
um (2 mils) tall insulating layers between the copper layers.
Thus, the overall inductance loop is smaller than in the first
layout. In Figure 6(a), the dead band can be clearly seen in
the dip occuring around -12 ns with turn on occuring at 0 ns.
The voltage rises to 12 V in 5 ns. Additionally, the small
inductance of the layout of Figure III can be seen in that the
ripple voltage at turn-on only rises to a peak of 14 V. The
falling transition can be seen in Figure 6(b) with the turn-off
time at a maximum of 5 ns for a 5 A load and minimum of
2 ns for a 20 A load.