Policy. When an STT-RAM line is frequently written and it
cannot migrate to SRAM, its WSC will finally saturate. At this
point, a tree-based comparator determines a STT-RAM block
in the same set with minimum WSC value. If its difference
with the saturation value is larger than a threshold (i.e. wear
leveling threshold), contents of these two STT-RAM lines are
exchanged. Fortunately, the tag-based addressing mechanism
in set-associative cache design simplifies such an exchange and
hence no address redirection is required. If the difference of
these two values is less than wear-leveling threshold, such a
replacement can be harmful. This situation implies that write
counts of the STT-RAM lines are in the same range and it is
not beneficial to sacrifice cache performance for the sake of
wear-leveling. If a line swapped or not, WSC counters of the
set are then decremented by the minimum WSC value. So, it
maintains relative write counts of STT-RAM lines within an
acceptable variance and reduces 40-bit counter overhead.
Policy. When an STT-RAM line is frequently written and itcannot migrate to SRAM, its WSC will finally saturate. At thispoint, a tree-based comparator determines a STT-RAM blockin the same set with minimum WSC value. If its differencewith the saturation value is larger than a threshold (i.e. wearleveling threshold), contents of these two STT-RAM lines areexchanged. Fortunately, the tag-based addressing mechanismin set-associative cache design simplifies such an exchange andhence no address redirection is required. If the difference of these two values is less than wear-leveling threshold, such areplacement can be harmful. This situation implies that writecounts of the STT-RAM lines are in the same range and it isnot beneficial to sacrifice cache performance for the sake ofwear-leveling. If a line swapped or not, WSC counters of theset are then decremented by the minimum WSC value. So, itmaintains relative write counts of STT-RAM lines within anacceptable variance and reduces 40-bit counter overhead.
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