Since the three gridded clocks, l2clk, drl2clk, and iol2clk, are
ultimately derived from the same reference, they are ratioed synchronous.
However, only l2clk–drl2clk and iol2clk-l2clk crossings
need to be addressed. The known periodic relationships of
the two interfaces are exploited to perform simplified domain
crossing, described next. Before proceeding, it is necessary to
make a distinction between clocks at the destination (suffixed
by l2clk) and those at the source (prefixed by pll_) in Fig. 12
and Fig. 14; as shown in Fig. 12, the latency may vary between
half to one and a half CMP cycles.