IDDQ test is based on measuring the current on supply lines (VDD, GND) of the circuit under test. The defects which
increase the IDDQ current are detected using a BICS inserted between the circuit under test and the ground. For CMOS
technologies which are of the micro-meter order, a single short between two nodes in the circuit can increase significantly the IDDQ current. Thus, the BICS can easily detect the presence of the fault [2-9]. However in [2] the authors show that at the nano-meter range (90 nm and below) the IDDQ testing is used to diagnose only the multiple bridging faults being able to create a resistive path between VDD and ground. Consequently, for the 65nm node technology, this testing approach will be appropriate only with respect to the multiple short faults occurring in the circuit under test and creating a resistive path between the power supply voltage and the ground.