A. CMOS FTFN Input Stage
To construct a constant-gm rail-to-rail input stage, Fig. 2
implementation of the input stage is obtained. To increase the
common-mode input voltage range, the N-channel input pair,
M1-M4, and the P-channel input pair, M2-M3 are placed in
parallel. By this way, at high common-mode voltage ranges
only N-channel input pair operates. On the other hand, with
the low common-mode voltage range only P-channel input
pair operates. With the intermediate common-mode voltages,
both P and Nchannel input pairs operate [9].
Since there are three regions of operation for the input
stage, there are three different regions for the total input
transconductance, gmT which can be expressed as