The DC voltages obtained through rectification of the outputs from secondary coils n21 and n22 are delivered to capacitor C11 in a parallel manner so as to be smoothed by the capacitor C11, and output V01 is obtained at output terminals 10 and 11. The DC voltage
obtained through rectification of the output from secondary coil n31 is supplied to capacitor C2] so as to be smoothed by capacitor C21 and is added to voltage V01
available at capacitor C2]. Voltage VH1, as the sum, is outputted from output terminals 10 and 12.