Second, the symbol appearing next to the Q and the outputs is the IEEE designation for a postponed output. In this case, it means Q does not change state until the clock makes an NT. In other words, the contents of the master are shifting into the slave on the clock NT, and at this time Q changes state.
To summarize: The master is set according to J and K while the clock is high; the contents of the master are then shifted into the slave (Q changes state) when the clock goes low. This particular flip-flop might be referred to as pulse-triggered, to distinguish it from the edge-triggered flip-flops previously discussed.
There are numerous pulse-triggered master-slave flip-flops in use today. However, because edge-triggered flip-flops have overcome the restriction of holding J and K static when the clock is high, most new designs incorporate edge-triggered devices. Some of the more popular pulse-triggered flip-flops you might encounter include the 7473, 7476, and 7478. Their more modern, edge-triggered counterparts include the 74LS73A, the 74LS76A, and the 74LS78A.
Example 8-9
The JK master-slave flip-flop in Fig. 8-28 has its J and K inputs tied to +Vcc, and a series of pulses (actually a square wave) are applied to its C input. Describe the waveform a Q.
Solution
Since J = K = 1, the flip-flop simply toggles each time the clock goes low. The waveform at Q has a period twice that of the C waveform. In other words, the frequency of Q in only one-half that of C. This circuit acts as a frequency divider — the output frequency is
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Fig. 8-29
equal to the input frequency divided by 2. Note that Q changes state on NTs of the clock. The waveform are given in Fig. 8-29.