Hardware support. We require a mechanism to monitor
number of write requests directed to each STT-RAM line for
wear-leveling at line granularity. Theoretically, we should keep
tracing the total number of write operations for each line. As,
the STT-RAM cell with 10
13
write endurance needs a 40-bit
counter to record the total number of writes. To reduce such an
area overhead, we use a small counter named Wear-level
Saturation Counter, WSC (Figure 2), instead and update it
periodically to track approximate wear-out of each STT-RAM
line. The same as the LSC, this wear-level saturation counter is
incremented at write requests.