7.2.2. DVMC Performance Overhead. DVMC can
potentially degrade performance in several ways. The
Uniprocessor Ordering checker requires an additional
pipeline stage, thus extending the time during which
instructions are in-flight and increasing the occupancy
of the ROB and the physical registers. Load replay
increases the demand on the cache and can cause additional cache misses. Coherence verification can degrade
system performance due to interconnect bandwidth
usage for inform messages. SafetyNet, the BER mechanism used during our tests, also causes additional interconnect traffic. Only the Allowable Reordering checker
does not have any influence on program execution, since
it operates off the critical path.