The variation of neutral and ion fluxes with varying radial position, shown in Fig. 2, results in a variation in the deposited oxide thickness, which in turn, causes the TSV parasitic capacitance to depend on the TSV position on the wafer. This is shown in Fig. 5 (bottom), where it becomes clear that the TSVs placed at locations exhibited to lower neutral and ion fluxes have an increased parasitic capacitance. The DC capacitance variation amounts to about 3% between wafer center and wafer rim. The frequency dependence of the TSV capacitance can be seen in Fig. 5 (top), where the simulation is performed using a boron-doped bulk silicon (2.15 1015 cm 3).