To generate a reset pulse on an nth cycle (times betWeen T11 and T13) of the ramp signal generating circuit 3, “control signal lam-current signal IL” must be a level betWeen “(control signal lam-current signal IL)a” and “(control signal lam-current signal IL)b”, as shoWn in FIG. 8. Namely, if “control signal lam-current signal IL” is smaller than “(control signal lam-current signal IL)a”, “con trol signal lam-current signal IL”
becomes smaller than “ramp signal Ramp3+ramp signal Ramp11” before the time T11, so that a reset pulse is generated at this timing. If “control signal lam-current signal IL” is larger than “(control signal lam-current signal IL)b”, “control signal lam-current signal IL” can not be smaller than “ramp signal Ramp3+ramp signal Ramp11” in the nth cycle, and a reset pulse is generated on and after an (n+1)th cycle. Accordingly, the generation of a reset pulse on the nth cycle