In the high power device packages, due to the
connection of the aluminum wire between chips and the
copper layer, and the connection between the chips and
power terminals, there is small parasitic inductances between
the output terminals and inner chips in modules. Generally,
there are two emitter terminals for high power IGBTs,
namely Kelvin emitter for the gate driver and the power
emitter for the power path. The inductor Ls1 is the sum of the
series parasitic inductances in DM module and the positive bus bar parasitic inductance. LeE is the parasitic inductance
between Kelvin emitter and the IGBT module power emitter.
Ls2 is the sum of the series parasitic inductances in the IGBT
module and the negative bus bar, excluding LeE. In the test
bench in Fig.2, for current commutation from diode DM to
switch SM, initially the load current IL flows though the
inductor load Lload, DM and Ls1, when switch SM is in the offstate.
By turning on SM, the load current IL begins to
commutate from diode DM to switch SM. The reverse
recovery current of diode DM, which is dependent to the chip
temperature, induces a measureable voltage veE on the
parasitic inductance LeE during the SM turn-on transition.
Compare with the measurement of dv/dt, auxiliary sensor
components are not required for the measurement of di/dt.
Because the parasitic inductance is a ten of nanohenries, veE
is tens of voltages under high load current. Once the
relationship between the voltage veE and the diode chip
temperature Tj is characterized, the chip temperature can be
extracted, facilitating a measurement circuit design, at the
emitter potential, without auxiliary high voltage or isolated
sensors. Thus the veE measurement circuit can be integrated
into gate drive circuit.
In the high power device packages, due to theconnection of the aluminum wire between chips and thecopper layer, and the connection between the chips andpower terminals, there is small parasitic inductances betweenthe output terminals and inner chips in modules. Generally,there are two emitter terminals for high power IGBTs,namely Kelvin emitter for the gate driver and the poweremitter for the power path. The inductor Ls1 is the sum of theseries parasitic inductances in DM module and the positive bus bar parasitic inductance. LeE is the parasitic inductancebetween Kelvin emitter and the IGBT module power emitter.Ls2 is the sum of the series parasitic inductances in the IGBTmodule and the negative bus bar, excluding LeE. In the testbench in Fig.2, for current commutation from diode DM toswitch SM, initially the load current IL flows though theinductor load Lload, DM and Ls1, when switch SM is in the offstate.By turning on SM, the load current IL begins tocommutate from diode DM to switch SM. The reverserecovery current of diode DM, which is dependent to the chiptemperature, induces a measureable voltage veE on theparasitic inductance LeE during the SM turn-on transition.Compare with the measurement of dv/dt, auxiliary sensorcomponents are not required for the measurement of di/dt.Because the parasitic inductance is a ten of nanohenries, veEis tens of voltages under high load current. Once therelationship between the voltage veE and the diode chiptemperature Tj is characterized, the chip temperature can beextracted, facilitating a measurement circuit design, at theemitter potential, without auxiliary high voltage or isolatedsensors. Thus the veE measurement circuit can be integratedinto gate drive circuit.
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