FIGURE 6-11
Biock Diagram of a Three-Decade Decimal BCD Counter
the state diagram of Fig. 6.9. Ql changes state after each clock pulse. Q~ complements every time Ql goes from I 10 O. as long as Qs = O. When Qs becomes 1. Q~ remains at O. Q4
complements every time Q2 goes from I to O. Qs remains at 0 as long as Q~ or Q-I is O. When
both Q2and Q4 become I. Q8complements when QJ goes from I to O. Qs is cleared on the next
transition of Qj.
The BCD counter of Fig. 6.10 is a decade counter. since it counts from0 to 9. To count in decimal
from0 to 99, we need a two-decade counter .To count from 0 to 999. we need a three - decade
counter. Multiple decade counters can be constructed by connecting BCD counters in cascade,
one for each decade. A three-decade counter is shown in Fig. 6.11. The inputs to the second and
third decades come from Qs of the previous decade. When Qs in one decade goes from I 10 O. it
trigger s the count for the next higher order decade ",'bile its own decade goes from 9 10 O.
6 - 4 SYNCHRONOUS COUNTERS
Synchronous counters arc different from ripple counters in that clock pulses arc applied to the
inputs of all flip-flops .A common clock triggers all flip-flops simultaneously. rather than one
at a time in succession as in a ripple counter. The decision whether a flip- flop is to be
complemented is determined from the values of the data inputs. such as T or J and K at the time
of the clock edge. If T ::: 0 or j ::: K ::: O. the flip-flop doe s not change state. If T ::: I or
J ::: K ::: I. the flip-flop complements.
The design procedure for synchronous counters was presented in Section 5.8. and the design
of a three-bit binary counter was carried out in conjunction with Fig. 5.31. In this section. we
present some typical synchronous counters and explain their operation