which write traffic is large and its access latency directly affects
processor performance. The motivation behind this work is the
non-uniformity of write accesses into different cache sets and
even within same cache set. This causes some sets to fail earlier
than others even in the presence of such a large number of
reliable write counts. In the domain of PRAM and flash
memories, wear leveling techniques [5,6,9] try uniformly
distributing writes, by remapping write-stressed data to lesswritten
sets. Almost
all
these
wear leveling
schemes
impose
considerable
overhead in
terms
of latency,
power,
and storage,
which
can harm
performance
and
energy-efficiency.