B. Lowering power and threshold voltages
Scaling the power supply voltage enables the reduction in
dynamic power dissipation.While reducing the power supply
of a chip might seem straightforward, nevertheless, it leads to
issues such as noises and possibly signal levels compatibility
problems in multichip systems using various supply voltages
[10]. Reduction in power supply, which also reduces threshold
voltage also increases static power during transistor off due
to leakage current. In [12], an analysis ofthe impact of
supply voltage scaling on the noise margin of CMOSNAND
was performed; it concludes that the supply voltage cannot
be scaled lower than 0.5 Vin order to keep logic state
consistency in the worst-case switching scenario. As threshold
voltage is reduced aswell, the transistor cannot be completely
turned off.