Another problem is that bare-metal message passing may lead to deadlocks—unless
more advanced hardware protocols or software libraries internally impose structured
communication protocols, both implying additional overheads. As an example, consider
wormhole routing on the TilePro 64. Wormhole routing describes a packet transfer
strategy, where pathways through the switching network are opened by the head of
the packet and remain open until the final flit of the packet is seen. The ramification of
this is that packets of other messages crossing a currently open path remain blocked
until this wormhole is closed. This alone does not result in deadlock as long as packets
transfer successfully. The problem arises when SRAM buffers reach capacity on a
receiving switch and its attached core is unable to drain the buffer. When this situation
occurs, a crossing packet will be stalledmid-flight, blocking the packet’s sender and any
other cores sending data that share any portions of that packet’s path. Consider two
tasks shown in Figure 1 transferring fixed-size buffers to each other concurrently. In
the Tilera architecture, the receiving tasks can buffer up to 127 words in a flit.However,
when the buffer becomes full, the switching network must wait until flits are drained
before transferring any remaining flits. Exchanging contiguous buffers exceeding 127
words will result in a deadlock (infinite blocking), not just for the two cores but also
affecting any messages going across this link between the two cores on some route.
Another problem is that bare-metal message passing may lead to deadlocks—unlessmore advanced hardware protocols or software libraries internally impose structuredcommunication protocols, both implying additional overheads. As an example, considerwormhole routing on the TilePro 64. Wormhole routing describes a packet transferstrategy, where pathways through the switching network are opened by the head ofthe packet and remain open until the final flit of the packet is seen. The ramification ofthis is that packets of other messages crossing a currently open path remain blockeduntil this wormhole is closed. This alone does not result in deadlock as long as packetstransfer successfully. The problem arises when SRAM buffers reach capacity on areceiving switch and its attached core is unable to drain the buffer. When this situationoccurs, a crossing packet will be stalledmid-flight, blocking the packet’s sender and anyother cores sending data that share any portions of that packet’s path. Consider twotasks shown in Figure 1 transferring fixed-size buffers to each other concurrently. Inthe Tilera architecture, the receiving tasks can buffer up to 127 words in a flit.However,when the buffer becomes full, the switching network must wait until flits are drainedbefore transferring any remaining flits. Exchanging contiguous buffers exceeding 127words will result in a deadlock (infinite blocking), not just for the two cores but alsoaffecting any messages going across this link between the two cores on some route.
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