In the nodal analysis of the previous sections we applied KCL at the nonreference nodes of the circuit. We shall now consider a related method known as mesh analysis, in which KVL is applied around certain loops in the circuit. As we shall see, in the case the unknowns in the resulting equations will be currents.
We shall restrict attention in this section to planar circuits, that is, circuit that can be drawn on a plane surface so that no elements or connecting wires cross. In this case, the plane is divided by the circuit diagram into distinct areas in the same fashion that the solid framework in a window separates and outlines each individual window pane. The closed boundary of each such window pane area is called a mesh of the circuit. Thus a mesh is a special case of a loop, which we consider to be any closed path of elements in the circuit passing through no node or element more than once. In other words, a mesh is a loop that contains no element within it.