Including a cache memory in a system improves its speed because there is a copy of useful memory data close at hand where they can be easily accessed. This is wonderful if there is only one processor, but it creates a serious problem if there may be several processors. The basic problem is easily stated: Correct locking relies on the existence of a single copy of the lock object to which all accesses are serialized; if caching creates several copies of the lock object, it is possible for more than one process to think that it has successfully locked the lock. A similar problem arises regarding the shared data held in memory. We need a scheme that guarantees that all processors will see the same memory contents when it is important. With value in caches, there must exist a mechanism to assure that all caches contain the same value for the same memory location. In other words, we wish for cache coherence.